TL;DR
- Third-generation High Bandwidth Memory standard ratified by JEDEC in January 2022.
- Per-stack bandwidth up to 819 GB/s (6.4 Gb/s per pin × 1,024 pins); per-stack capacity up to 24 GB at launch.
- Used in NVIDIA H100, AMD MI300X, and many other 2022-2024 accelerators.
- Superseded by HBM3e and (in 2025) HBM4 at the leading edge but remains widely deployed.
Overview#
HBM3 is the third-generation High Bandwidth Memory standard. JEDEC published the JESD238 specification in January 2022, codifying a 1,024-bit-wide per-stack interface running at up to 6.4 Gb/s per pin — 819 GB/s of bandwidth per stack. SK hynix, Samsung and Micron all produced HBM3 stacks, with SK hynix dominating shipments through 2023-2024.
The first widely-deployed HBM3 accelerator was NVIDIA's H100 (80 GB / 3.35 TB/s, five active stacks). AMD followed with MI300X (192 GB / 5.3 TB/s, eight stacks). HBM3 is the memory standard behind the bulk of 2022-2024 large-model training and inference.
Specifications#
| Metric | HBM3 |
|---|---|
| JEDEC standard | JESD238 (Jan 2022) |
| Pin speed | Up to 6.4 Gb/s |
| Interface width | 1,024 bits per stack |
| Bandwidth per stack | Up to 819 GB/s |
| Capacity per stack | 8-24 GB (8-high, 12-high) |
| Channels per stack | 16 |
| Voltage | 1.1 V |
| Process | 10 nm-class DRAM |
Architecture Notes#
Each HBM3 stack consists of multiple DRAM dies (typically 8 or 12 high) stacked vertically and connected by through-silicon vias to a base logic die. The stack is integrated on a silicon interposer alongside the host processor — usually a GPU — using 2.5D packaging (CoWoS on NVIDIA, Foveros/CoWoS on AMD).
The 1,024-bit interface is wide and slow rather than narrow and fast. This trade gives HBM its bandwidth-per-watt advantage over GDDR — moving bits short distances on a wide bus is dramatically more efficient than running fewer wires at multi-gigabit speeds across a PCB.
HBM3 raised channels per stack from 8 (HBM2e) to 16, improving access concurrency and reducing tail latency for irregular access patterns.
Where HBM3 Lives in 2026#
- Widely deployed in H100, MI300X, MI250, MI250X, and most 2022-2024 frontier accelerators.
- Still produced and consumed at substantial volume even as HBM3e and HBM4 ramp.
- Secondary market and amortised on-prem deployments will keep HBM3 relevant for years.
Pitfalls#
- Supply: HBM3 production was constrained through 2023-2024; lead times of 26-52 weeks were normal.
- Capacity per stack: 24 GB max (12-high) cap; very-large per-GPU memory requires multiple stacks and complex packaging.
- Thermal: HBM stacks share a thermal envelope with the host processor — cooling design must account for them.
Comparison to HBM2e and HBM3e#
HBM3 over HBM2e: bandwidth nearly doubled (819 GB/s vs 460 GB/s per stack), capacity increased, voltage dropped slightly.
HBM3e over HBM3: pin speed up to 9.2 Gb/s, bandwidth per stack to ~1.2 TB/s, capacity to 36 GB (12-high). HBM3e is the practical successor in 2025-2026 accelerators.
References
- JEDEC HBM3 Standard (JESD238) · JEDEC
- SK hynix HBM3 Product Information · SK hynix